The present invention relates to a MOS type semiconductor device formed on an insulating substrate.
It is known to persons skilled in the art to form an integrated circuit containing MOS transistors on a silicon epitaxial layer formed on an insulating substrate made of material with a spinel structure or sapphire. Such an integrated circuit is generally called an SOS IC. The SOS IC thus formed has many advantages: the transistors may be isolated by an insulating material; and a complementary MOS transistor circuit may be formed without forming a well structure. The latter feture provides a small parasitic capacity of interconnection and thus a small power delay product (t-p product). Further, the SOS IC does not suffer from a latch-up phenomenon which arises from the parasitic bipolar transistor and results in an erroneous operation or breakdown of the semiconductor device. Those advantages are very useful in fabricating high density MOS integrated circuits.
An exemplar of the SOS IC containing MOS transistors with a structure as shown in FIGS. 1 and 2 is known in this field. A diagram of FIG. 2 is a cross section taken along line II--II in FIG. 1. As shown, an island of a semiconductor layer 14 is provided on an insulating substrate 10 of sapphire, being covered with an insulating film 12. The island 14 comprises a source region 18 of p.sup.+ type, a drain region 20 of p.sup.+ type, and a substrate region 16 of n.sup.- type sandwiched between the source and drain regions 18 and 20. The source region 18 and the drain region 20 are in contact with the insulating substrate 10 of sapphire. A gate electrode 24 made of poly-silicon is formed above a channel region between the source region 18 and the drain region 20, with a gate insulating film 22 interposed therebetween.
In the SOS IC of the prior art, the substrate region 16 under the channel forming region of the MOS transistor is separated from the source and drain regions 18 and 20 by pn junctions. Further, it is separated from the insulating substrate 10, the insulating film 12 and the gate insulating film 22. Thus, the substrate region 16 of the MOS transistor of SOS IC is in a floating state. For this reason, it is impossible to supply potential from exterior to the substrate region 16. Therefore, the prior SOS IC has the following disadvantages:
(a) A kink appears in an I.sub.D -V.sub.D characteristic which is a relationship of drain current I.sub.D versus drain voltage V.sub.D with a parameter of gate voltage.
(b) When a charge pumping phenomeon takes place in the substrate region 16 in a floating state, a reverse bias voltage with respect to the source potential is applied to the substrate region 16. Therefore an effective threshold voltage V.sub.TH of the MOS transistor shifts to an enhancement mode side (i.e. .vertline.V.sub.TH .vertline. increases).
(c) When a forward bias voltage with respect to the source potential is applied to the substrate region 16 in the floating state, the effective threshold voltage of the transistor shifts to a depletion mode side (i.e. .vertline.V.sub.TH .vertline. decreases).
Of those disadvantages, particularly the charge pumping phenomenon in item (b) causes an electrical characteristic of the MOS transistor on the insulating substrate 10 to depend upon a frequency of a drive signal. The charge pumping phenomenon further remarkably reduces a conductance of the MOS transistor formed on the insulating substrate 10. Particularly, when the previous driving states of MOS transistors have been different from each other, even if the MOS transistors have the same dimension, this phenomenon causes a difference between the conductances of the two transistors. Therefore, if this phenomenon should occur in a sense amplifier circuit having the MOS transistors of the balance type load, an erroneous operation may take place. If it should occur in a MOS transistor for a transfer gate, a circuit delay may take place.
There has been proposed an SOS IC as shown in FIG. 3 which supplies potential to the substrate region 16 so as not to render the substrate region 16 the floating state. As shown, an end portion 26 of the n.sup.- type substrate region 16 as viewed in the channel width direction and an end portion 28 of a gate electrode 24 as viewed in the channel width are expanded in the channel length direction. An n.sup.+ type impurity region 30 of the same conductivity type as that of the substrate region 16 is coupled with the end portion 26 of the substrate region 16. Potential is applied to the substrate region 16, through an electrode 32 connected to the n.sup.+ type impurity region 30. The end portion 26 of substrate region 16 is widened in a channel longitudinal direction for compensating for a displacement of the joint between the n.sup.+ type impurity region 30 and the substrate region 16.
In the case of the SOS IC with such a structure, however, it is difficult to effectively supply potential to the substrate region 16 of the MOS transistor with a large channel width W. Specifically, the potential is effectively applied from the n.sup.+ type impurity region 30 to one end of the substrate region 16 adjacent to the n.sup.+ type impurity region 30 (a portion of the substrate region from which potential is taken out). However, the potential supply to the other end of the substrate region 16 is not effective, because the other end of the substrate region 16 is apart from the impurity region 30 by a channel width W. A resistivity .rho. of the substrate region 16 is relatively large, and a large gate capacity is generally present between the substrate region 16 and the gate electrode 24. Therefore, it is very difficult to keep the potential of the entire substrate region 16 at the same potential as that of the impurity region 30. The resistance R of the substrate region 16 is given by the following formula (1) EQU R.perspectiveto.W.multidot..rho./T.multidot.(L-.DELTA.L) (1)
where .rho. is the resistivity of the substrate region 16, W is the channel width, L is the channel length, .DELTA.L is a decrement of the channel length due to depletion layers at the junction between the substrate region 16 and the source region 18, and a junction between the substrate region 16 and the drain region 20, and T is a thickness of the substrate region 16.
A static capacitance (gate capacitance) between the substrate region 16 and the gate electrode is given by the following formula (2) EQU C.perspectiveto..epsilon..sub.ox .multidot.W.multidot.(L-.DELTA.L)/t.sub.ox ( 2)
where t.sub.ox is a thickness of a silicon oxide film and .epsilon..sub.ox is a dielectric constant of the silicon oxide film.
From the above formula (1) and (2), a time constant RC is given by a relation (3), EQU RC.perspectiveto..epsilon..sub.ox .multidot.W.sup.2 .multidot..rho./t.sub.ox .multidot.T (3)
For example, .rho.=0.5 .OMEGA..multidot.cm, t.sub.ox =500 .ANG., T=0.5 .mu.m. In this case, RC.perspectiveto.7.times.W.sup.2 sec. When the channel width W is 10 .mu.m, RC.perspectiveto.0.7 nsec. When the channel width W is 50 .mu.m, RC.perspectiveto.17.5 nsec.
Thus, when the MOS transistor has a large channel width W, even if the potential is applied from the end of the transistor to the substrate region 16, the potential delayed by rather a large time constant RC is obtained at the other end of the transistor as shown in FIG. 3. Therefore, the potential of the substrate region 16 can not effectively be controlled.
IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. ED-25, No. 8, August, 1978, p. 910 discloses a means for supplying potential to the substrate region. In the means disclosed, when the channel length L is short, for example, L.perspectiveto.2 .mu.m, it is necessary to set an accuracy of masking to L/2 or less for forming the impurity region of n.sup.+ type. If not so done, the n.sup.+ type impurity region is superposed over the drain region and the drain junction capacity between the drain region and the gate electrode increases, or the substrate region can not be connected with the n.sup.+ type impurity region. In order to limit the masking accuracy to be L/2 or less, the mask must be formed with extremely high precision, and an expensive mask aligner is needed.